Pipeline Implementation of Peer Group Filtering in FPGA
Keywords:
Colour image processing, reconfigurable systems, FPGA, parallel algorithmsAbstract
In the paper a parallel FPGA implementation of the Peer Group Filtering algorithm is described. Implementation details, results, performance of the design and FPGA logic resources are discussed. The PGF algorithm customized for FPGA is compared with the original one and Vector Median Filtering.Downloads
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Published
2012-10-03
How to Cite
Kryjak, T., & Gorgon, M. (2012). Pipeline Implementation of Peer Group Filtering in FPGA. Computing and Informatics, 31(4), 727–741. Retrieved from http://147.213.75.17/ojs/index.php/cai/article/view/1102
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Articles