Fast Hardware Implementations of Static P Systems

Authors

  • Juan Quiros ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla
  • Sergey Verlan LACL, Departement Informatique, Universite Paris Est, 94010 Creteil
  • Julian Viejo ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla
  • Alejandro Millan ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla
  • Manuel J. Bellido ID2 Group, Department of Electronic Technology, University of Seville, 41012, Sevilla

Keywords:

Reconfigurable hardware, P systems, static P systems, FPGA, membrane computing, parallel implementations of membrane computing, simulator of membrane computing, hardware implementations of membrane computing, parallel implementations of static P systems

Abstract

In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as words of some regular context-free language. Then, using formal power series it is possible to obtain the number of possibilities and select one of them following a uniform distribution, in a fair and non-deterministic way. According to these ideas, we yield an implementation whose results show an important speed-up, with a strong independence from the size of the P system.

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Published

2016-11-02

How to Cite

Quiros, J., Verlan, S., Viejo, J., Millan, A., & Bellido, M. J. (2016). Fast Hardware Implementations of Static P Systems. Computing and Informatics, 35(3), 687–718. Retrieved from http://147.213.75.17/ojs/index.php/cai/article/view/1665

Issue

Vol. 35 No. 3 (2016): Computing and Informatics

Section

Articles