Implementation of a RANLUX Based Pseudo-Random Number Generator in FPGA Using VHDL and Impulse C

Authors

  • Agnieszka Dąbrowska-Boruch AGH University of Science and Technology, Department of Electronics, al. A. Mickiewicza 30, 30-059 Kraków, Poland & ACC CYFRONET AGH, ul. Nawojki 11,30-950 Kraków
  • Grzegorz Gancarczyk AGH University of Science and Technology, Department of Electronics, al. A. Mickiewicza 30, 30-059 Kraków, Poland & ACC CYFRONET AGH, ul. Nawojki 11,30-950 Kraków
  • Kazimierz Wiatr AGH University of Science and Technology, Department of Electronics, al. A. Mickiewicza 30, 30-059 Kraków, Poland & ACC CYFRONET AGH, ul. Nawojki 11,30-950 Kraków

Keywords:

RANLUX, FPGA, PRNG, HPC, HPRC, VHDL, Impulse C

Abstract

Monte Carlo simulations are widely used e.g. in the field of physics and molecular modelling. The main role played in these is by the high performance random number generators, such as RANLUX or MERSSENE TWISTER. In this paper the authors introduce the world's first implementation of the RANLUX algorithm on an FPGA platform for high performance computing purposes. A significant speed-up of one generator instance over 60 times, compared with a graphic card based solution, can be noticed. Comparisons with concurrent solutions were made and are also presented. The proposed solution has an extremely low power demand, consuming less than 2.5 Watts per RANLUX core, which makes it perfect for use in environment friendly and energy-efficient supercomputing solutions and embedded systems.

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How to Cite

Dąbrowska-Boruch, A., Gancarczyk, G., & Wiatr, K. (2014). Implementation of a RANLUX Based Pseudo-Random Number Generator in FPGA Using VHDL and Impulse C. Computing and Informatics, 32(6), 1272–1292. Retrieved from http://147.213.75.17/ojs/index.php/cai/article/view/2165

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